According
to the ITRS roadmap, the number and complexity of application
accelerators (video codec, wireless modem) will continue to
increase along with the demand for better, faster, cheaper products.
To remain competitive, dramatic productivity gains are required.
The only way to achieve these gains is by elevating the level
of abstraction for design significantly above RTL yet maintaining
the Quality of Results (QoR) comparable to manual design. The
higher the abstraction level and better the QoR provided by
algorithmic synthesis tools, the bigger the productivity gains
will be.
According to EDA industry analyst, Gary Smith, the next 18 months
will see the consolidation in C-based synthesis tools
where multi-level hierarchical synthesis will replace older technologies
and design teams around the world will see the transition from RTL to
C/SystemC based design. This topic of C synthesis has also been
raising awareness on the latest DeepChip-ESNUG postings. Historically,
Japan and Europe have led the charge on this focus but this is rapidly
becoming a worldwide movement.
PICO Algorithmic Synthesis creates application accelerators from
untimed C for complex processing hardware (video, imaging, wireless
and security).The PICO Platform offers the highest possible level of
abstraction for large designs and has been proven to provide huge productivity
gains on the largest production designs, not just on small blocks. PICO
delivers QoR competitive to manual design using a unique parallelizing
compiler and multi-level hierarchical abstraction . The
PICO platform has several additional unique technologies to drive optimal
QoR. Examples include multi-level power optimization, advanced hardware
sharing among blocks and intuitive performance feedback. PICO enables
high-level verification at the C level delivering 100x speed-up.
The PICO platform has been adopted and deployed by leading customers
in production designs for multiple tapeouts.
Only the
PICO Platform delivers the best productivity through
abstraction and QoR.
According
to the ITRS roadmap, the number and complexity of application
accelerators (video codec, wireless modem) will continue to
increase along with the demand for better, faster, cheaper products.
To remain competitive, dramatic productivity gains are required.
The only way to achieve these gains is by elevating the level
of abstraction for design significantly above RTL yet maintaining
the Quality of Results (QoR) comparable to manual design. The
higher the abstraction level and better the QoR provided by
algorithmic synthesis tools, the bigger the productivity gains
will be.
According to EDA industry analyst, Gary Smith, the next 18 months
will see the consolidation in C-based synthesis tools
where multi-level hierarchical synthesis will replace older technologies
and design teams around the world will see the transition from RTL to
C/SystemC based design. This topic of C synthesis has also been
raising awareness on the latest DeepChip-ESNUG postings. Historically,
Japan and Europe have led the charge on this focus but this is rapidly
becoming a worldwide movement.
PICO Algorithmic Synthesis creates application accelerators from
untimed C for complex processing hardware (video, imaging, wireless
and security).The PICO Platform offers the highest possible level of
abstraction for large designs and has been proven to provide huge productivity
gains on the largest production designs, not just on small blocks. PICO
delivers QoR competitive to manual design using a unique parallelizing
compiler and multi-level hierarchical abstraction . The
PICO platform has several additional unique technologies to drive optimal
QoR. Examples include multi-level power optimization, advanced hardware
sharing among blocks and intuitive performance feedback. PICO enables
high-level verification at the C level delivering 100x speed-up.