In the various domains of multimedia, imaging, wireless, security and communications, constant consumer demand for faster and cheaper products is putting design teams under huge pressure. To compete in these markets, designers are focusing on the increasingly complex algorithms that differentiate the end product. But in order to be successful, teams must also be able to meet aggressive deadlines and power, performance and area (PPA) targets, and be capable of reacting to late changes in spec. The only way for design teams to retain competitiveness is to migrate to a higher level of abstraction.

PICO Express algorithmic synthesis was developed by Synfora to deliver efficient hardware from untimed C algorithms. This method enables the designer to work at a higher level of abstraction, with the added possibility of re-using IP targeted against specific design criteria.

Figure 1. Many modern products are defined by multiple complex algorithms for features and performance. As a result, complexity is making costs and time unmanageable for design teams.

How does PICO Express work?
The PICO technology is based on a sophisticated compiler which analyzes the sequential C code, finding and exploiting parallelism at multiple levels.

PICO Express takes a C algorithm and a set of design requirements (clock frequency, throughput target and technology file) and creates a series of implementation models (RTL, SystemC). PICO’s ability to exploit parallelism at multiple levels enables it to find the most efficient implementation of the algorithm necessary to meet performance targets. PICO Express identifies the appropriate level of parallelism to match the throughput (performance) requirements, and creates the hardware that will execute the algorithm in the time specified by the user. This method can be applied to a wide variety of algorithms.

Figure 2. PICO Express enables the designer to explore and create efficient hardware from an untimed C algorithm. PICO Express creates RTL and SystemC models and testbenches. PICO Express creates scripts for synthesis and supports industry standard verification and physical design tools.

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What else does PICO Express do?
Hardware - PICO Express creates an application engine as hardware to execute the algorithm, along with standard interfaces and subsystem control to ensure rapid and consistent integration into the fabric of the SoC.

Verification - PICO Express creates testbenches for the RTL which recreate the C tests and verify that the behavior of the C and RTL are identical. PICO Express also allows for testing and validation of properties (stalling behavior, FIFO sizing) of the hardware that are not captured in the C algorithm.

Interfaces - PICO Express provides scripts and interfaces to industry standard verification and physical design flows.

Driver - PICO Express creates a software drive to enable software configuration and control of the application engine (hardware).

Figure 3. An SoC comprises StarIP (CPU), Memory, Connectivity and control (USB, memory controller) and Application engines (video decoder, wireless modem). It is the application engines that execute the core functionality, defining and differentiating the SoC.

What are the key features of PICO Express?

• Best Implementation: Advanced compiler can exploit parallelism at multiple levels to find the best implementation
• Best Quality of Results: Sophisticated memory analysis to produce best QoR even for large algorithms
• Optimal Efficiency: Global analysis of complex networks of sub-blocks to balance the overall system for optimal efficiency

In addition, Synfora will team with you to provide . . .

• Multiple levels of training
• Domain knowlegeable expertise

Figure 4. PICO Express GUI allows the designer to explore multiple alternatives, find and correct recurrences that limit performance, and cross probe between C and RTL to understand the implementation of the algorithm in hardware..

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What are the key benefits of PICO Express?

• Reduced Design Time: PICO Express algorithmic synthesis reduces development time and allows the designer to reuse IP targeted against specific design criteria.
• Improved Design Quality: Automatic design space exploration allows designers to find the best implementation for the end application. Streaming data, multiple local memories and powerful compiler analysis minimize memory and bus bandwidth bottlenecks.
• Reduced Verification and Integration Time:
  • PICO hardware Architecture uses previously verified blocks and correct-by-construction configuration
  • Automatic creation of test benches validates the RTL
  • Successive comparisons are made against the reference throughout the PICO Express flow

What can I expect to gain from using PICO Express?
PICO Express algorithmic synthesis enables design teams to reduce design time significantly, to react to late changes in requirements and to focus on differentiation at the algorithmic level. As a result of using PICO Express, you will see a significant (2-5x) reduction in designing the hardware for the first time and an even greater reduction (10-20x) when creating a derivative based on the original algorithm. Synfora has consistently set the standard in algorithmic synthesis for capacity, flexibility and efficiency. Synfora has also developed an engagement methodology that minimizes the risk of deployment while maximizing the benefits. The company is building bridges to the future, both in terms of developing the ecosystem with other partners and continuing to push the state-of-the-art in algorithmic synthesis.

Summary

• PICO Express creates efficient hardware from C algorithms for SoCs defined and differentiated by algorithms.
• Synfora has consistently led the field in terms of capacity, flexibility and efficiency.
• Synfora’s engagement approach minimizes deployment risk while maximizing benefits.
• Synfora continues to build bridges to the future by partnering with other leaders in the ecosystem and continuing to drive the state-of-the-art for algorithmic synthesis.

By choosing Synfora and PICO Express, your team will be able to deploy algorithmic synthesis at the lowest risk with the highest rewards. As a result, you will be able to continue to differentiate your SoCs despite increasing algorithmic complexity.

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