Overview
Design teams are under growing pressure to create faster, cheaper, better products. Increasingly power consumption is becoming the most critical differentiator, and designers struggle to indentify where power is being consumed and how to reduce the power consumption. PICO Extreme Power is the industry’s first algorithmic synthesis tool that automatically optimizes the power consumption at the system level using a variety of techniques including automatic multi-level clock gating insertion along with the necessary control logic. PICO Extreme Power has delivered savings of up to 50% using this technique.

About the PICO platform
Synfora’s  PICO Platform creates application accelerators from sequential, untimed C algorithms for complex processing hardware in video, imaging, wireless and security domains. PICO generates RTL, verification test-benches, SystemC models at multiple levels of accuracy, software driver and interoperability scripts.

The PICO Platform delivers huge productivity gains by creating application accelerators at the highest level of abstraction with QoR competitive with manual design. PICO’s high QoR is based on a unique parallelizing compiler, using multi-level hierarchical abstraction and IP reuse. PICO platform has been adopted and deployed by leading customers in production designs with multiple tapeouts.

 

PICO Extreme Power introduces a major innovation in algorithmic synthesis -- automatic multi-level clock gating insertion – to enable power optimizations at the system level and eliminate all manual work. In traditional RTL (Register Transfer Language) design methodologies, inserting clock gating at a block level is usually a manual effort because it requires the knowledge of when the block is inactive. Using PICO Extreme Power, the designer uses directives to specify where to insert clock gating, and PICO does the rest automatically. In all cases the user can make changes without having to impact the algorithm or the code.

As a result, PICO Extreme Power allows designers to retain all the productivity benefits of automated synthesis and verification, including reduced design and verification time and the ability to react very rapidly to changes in the design specification, while optimizing the IC power consumption

Key Capabilities

Coarse-Grain Clock Gating: PICO Extreme Power builds the clock gating infrastructure to turn off complete blocks at the top level of the design; for example, to turn off the complete quantize stage of an imaging pipeline. Of critical value is the control logic that will indicate when the block can be turned off. PICO Extreme Power understands exactly when every block is active versus idle, so the clock enable logic can be designed automatically. There is no need for time consuming manual analysis to decide “when” a block can be turned off.

Fine-Grain Clock Gating: There may be significant power saving byturning off only portions of a block, for example a TCAB used in a top level block or in another TCAB.  Like coarse-grain clock gating, PICO Extreme Power
automates clock gating insertion for TCABs hierarchically.

Automatic Functional Verification: PICO Extreme Power provides automatic functional verification to check the sequencing of clock gating for both coarse-grained as well as fine-grained clock gating.

Integration with downstream tools: PICO Extreme Power automatically generates waveforms in VCD/FSDB formats to enable power measurement in down-stream power analysis tools.

 

Key Benefits

• Significant power savings: >50% for some applications
  • Power savings are over-and-above what can be achieved with gate-level clock gating in
    down-stream tools
    
    
• Fully automated and easy to use
  • Eliminates time-consuming manual
    effort to insert clock gating, its verification
    and power measurement with down-stream tools

 

 

Results

1. The following table shows the power savings achieved on two customer designs using PICO Extreme Power. Most of the benefits in the video design come from coarse-grained clock gating, whereas most of the benefits in the wireless design come from fine-grained clock gating. Although it is not always possible to predict which technique will deliver the best results, PICO Extreme Power makes it easy to rapidly create the designs and measure the results.

   	Fine-Grained Clock gating	Coarse + Fine-Grained Clock gating
   Video design	50%	53%
   Wireless design	4.73%	22.4%

2. A design for a low density parity check (LDPC) decoder for the next generation wireless handset SoC achieved 23.5% reduction in dynamic power over an identical design using a standard flow.
   
3. An evaluation of the effectiveness of the approach using 8 complex applications in video, imaging and wireless domains demonstrated the following:
   • Up to 50% reduction in dynamic power for executing a single task and up to 30% savings while executing a large number of tasks
   • Average power reduction of 22% for a single task and 15% over multiple tasks

 

For more information, contact:
E-mail:  info@synfora.com
Website: www.synfora.com
Phone: (650) 314 0500 x110
Fax: (650) 314-0501