Overview
Design teams are under growing pressure to create faster, cheaper products. Complex algorithms on silicon differentiate the SoC, but implementing them is expensive and time-consuming. Synfora’s PICO Express provides proven, effective and low-risk algorithmic synthesis technology. Now PICO Extreme moves you to the next level with algorithmic synthesis for larger, more complex sub-systems.
About the PICO Platform
Synfora’s PICO platform automatically creates complex hardware sub-systems from sequential untimed C algorithms. Tools based on the PICO platform allow designers to explore programmability, performance, power, area and clock frequency. In addition, tools developed with the PICO platform technology will reduce time to market by eliminating months of manual RTL design and by providing a comprehensive and robust verification and validation environment, which includes SystemC TLM support and automatic RTL testbench creation.
PICO platform tools support SoC and FPGA flows enabling designers to build a library of re-usable algorithmic IP that can rapidly be deployed on a wide range of silicon technologies.
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PICO Extreme
PICO Extreme represents a major advance in algorithmic synthesis. PICO Extreme introduces a major technology innovation (TCABs), an advanced clock gating scheme for reduced power consumption, data extraction and export for C-RTL equivalence checkers, and an OCP-IP compliant host interface. PICO Extreme algorithmic synthesis enables the implementation of dramatically larger and more complex sub-systems, using a recursive system composition methodology. PICO Extreme reduces runtime and achieves an unprecedented quality of results including reduced power.
Key Innovation: TCABs
PICO Extreme enables a recursive system composition methodology. This approach is itself enabled by Synfora’s innovative Tightly Coupled Accelerator Blocks (TCAB) technology.
TCABs are C procedures that can be designed and verified standalone. The PICO compiler then automatically integrates and schedules these blocks as if they were primitive computing elements. TCABs can be repeated to an arbitrary depth, so that a building block can contain multiple building blocks.
Recursive system composition is the ability to build the system by using a set of customized building blocks, which the compiler then composes into a system by integrating and scheduling the custom building blocks with the native computing units.
This approach, which is very familiar to hardware designers, enhances the ability of the compiler to find better optimization, improving performance and reducing area. In addition, the pre-created blocks ensure that the runtime is reduced.
Area can be reduced by 10% or more and runtimes reduced 5x or more, depending on the application.
Advance: Sophisticated clock gating scheme to improve power efficiency.
Today clock gating is performed at a low level and many clock gating cells are required, all reducing power efficiency. PICO Extreme enables a designer to gate the clock of a complete processing function (loop nest) as a single entity, halting any activity within the processing function (including the clock tree) and only requiring one clock gating cell. The user inserts the clock-gating cell and PICO Extreme generates the enable signal automatically (ie, when each PA can be safely gated). This simplifies the scheme and saves power.
Advance: Extraction and export of C-RTL mapping information.
This feature enables C-RTL equivalence-checking tools to verify the equivalence between PICO-generated RTL and C. The information includes (for each C loop nest and its corresponding RTL block):
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design latency/throughput
- bit-accurate mapping of external C variables and stream functions to RTL block interfaces including scalar, stream and memory ports
- bit-accurate mapping of internal C variables to RTL wires, registers and memory objects
- additional control information for initialization and execution of loops in hardware
Creation of OCP-IP compliant host interface:
PICO Extreme IP can create software drivers and interface to the host that enable the sub-system to be controlled from a master processor using memory-mapped IO. Previously, the host interface was a Synfora native format; now an OCP-IP compliant interface is also available.
PICO Extreme Key Features
- TCAB technology enables recursive system composition
- Advanced clock gating scheme
- Extracts and exports C-RTL mapping information for equivalence-checking
- Creates OCP-IP compliant interfaces
- Full training and domain-knowledgeable support given
PICO Extreme Key Benefits
- Significantly reduced runtime for larger designs
- Reduced area and power consumption
- Improved hierarchical verification and validation
- Familiar hardware design style
What can I expect to gain from using PICO Extreme?
PICO Extreme reduces time to market by eliminating months of manual RTL design and providing a comprehensive and robust verification and validation environment. PICO Extreme supports SoC and FPGA prototyping flows and enables designers to build a library of re-usable algorithmic IP for a wide range of silicon technologies.
Synfora – premier provider of algorithmic synthesis for SOC and FPGAs
The company has a three-pronged focus:
- Strengthen its lead on algorithmic synthesis technology.
PICO Extreme demonstrates key advances, reflecting the company’s determination to enable efficient results from complex algorithms through technology innovation and leadership.
- Focus on customer deployment.
Synfora dedicates domain-knowledgeable engineers to teach and assist in deploying algorithmic synthesis on challenging projects that demonstrate the benefits of moving to a higher level. This focus provides the best way of transferring practical knowledge to the user.
- Building bridges to the future.
Synfora is collaborating with industry leaders such as Coware, Synopsys, Cadence, Sequence and others to provide an integrated flow. The successful deployment of an ESL methodology depends on linking algorithmic synthesis to other ESL modeling and analysis tools. Synfora has already built reference flows with key suppliers and will continue to spearhead this effort.
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