- Synthesis of untimed C algorithms with quality of results comparable to hand design
- Productivity increases of 5-20X or more
- Integrated with common synthesis and simulation tools
- Automatic generation of RTL, SystemC models, testbench, and software driver
- Capable of handling large, complex designs
- Design exploration for optimal implementation
- System-aware implementation
Synthesis of C Algorithms With Hand-Design Quality
In the various domains of multimedia, imaging, wireless, security and communications, constant consumer demand for faster and cheaper products is putting design teams under huge pressure. The availability of powerful and low-cost FPGAs provides opportunities for new differentiated products. FPGAs provide a wide range of solutions from low-cost, powerful, flexible compute accelerators to comprehensive programmable systems-on-a-chip. In order to effectively use these devices, design teams need to be able to explore and rapidly deploy algorithms in an FPGA. PICO Express FPGA synthesizes efficient FPGA hardware from an untimed C algorithm, reducing the engineering cost and time and enabling design teams to react rapidly to new opportunities or changes in requirements.
Faster Design of FPGA Application Engines
Typical systems consist of a processor, memory, various pieces of standard IP for such things as controllers and interfaces, and critical algorithms. While much of the real estate goes to the standard items, most of the system’s key unique value resides in those critical algorithms. Expressed in C and implemented in hardware, the algorithms become application engines, and may need to be tuned and optimized late in the design cycle.
PICO Express FPGA synthesizes algorithms into a hardware application engine, along with standard interfaces and subsystem control to ensure rapid and consistent integration into rest of the system. The FPGA can be a standalone application engine that interfaces with other elements on the board, or it can be the entire processing platform, incorporating not only the application engine, but the processor, memory, and other IP as well. Last-minute changes to the algorithms can be synthesized into hardware in minutes, keeping such changes from delaying production.
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| PICO Express FPGA synthesizes efficient hardware from an untimed C algorithm. The resulting hardware can either be a standalone accelerator or a part of a system FPGA |
The Most Advanced Algorithmic Synthesis for Xilinx Virtex and Spartan Devices
PICO Express FPGA takes a C algorithm and a set of design requirements (clock frequency and throughput target) and creates a series of implementation models (RTL, SystemC). PICO Express FPGA’s ability to exploit parallelism at multiple levels enables it to find the most efficient implementation of the algorithm necessary to meet performance targets. PICO Express FPGA identifies the appropriate level of parallelism to match the throughput (performance) requirements, and creates the hardware that will execute the algorithm in the time specified by the user. PICO Express FPGA can be applied to a wide variety of algorithms.
PICO Express FPGA implementation has been optimized for Xilinx devices through characterization, Quality of Results (QoR) enhancements, and memory handling. Synfora has done a thorough characterization of the Virtex-4, Virtex-5, and Spartan-3 devices, based on a framework using Xilinx and Synplicity tools, to create models that are used by PICO Express FPGA to ensure that the synthesized RTL will meet the design’s performance requirements. Extensive analysis of benchmark designs has been performed to improve the scheduling algorithm, map efficiently to DSP48 units, and to provide cell and interconnect delays and provide accurate estimates of resource costs. Special efforts have been made to take advantage of the dual-port Block RAMs, allowing direct host access using the second port.
Wide Range of Applications
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Algorithms drive new standards and create new products in multiple domains. |
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PICO technology has been production proven in multiple domains. PICO Express FPGA synthesized complex algorithms into hardware of similar quality to hand crafted implementation. |
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PICO Express FPGA creates multi-block hardware from a single algorithm. Not only does PICO Express FPGA ensure that complex data flows are synchronized correctly, but also creates testbenches and SystemC models for the complete engine. Any changes to the algorithm are automatically reflected in the multiple models and test environments. |
PICO Express FPGA Fits Standard Flows
Explore: PICO Express FPGA includes a powerful design space exploration capability that creates multiple implementations, provides area and performance estimates, and allows tradeoffs to be evaluated, yielding a solution that best meets the system needs.
Synthesize: PICO Express FPGA generates optimized RTL and the necessary models and testbenches to ensure both that the RTL is correct and to demonstrate that the generated engine operates properly in the system.
Verify: PICO Express FPGA creates models and testbenches that can be verified using industry standard verification tools. In addition, PICO Express FPGA allows the algorithm implementation to be viewed and cross-probed with the algorithm code, providing confidence that the algorithm is operating correctly and efficiently.
Create an FPGA bitstream: The Xilinx ISE tools take the synthesized RTL and create a bitstream for an FPGA application engine. When creating an entire processing platform inside the FPGA, PICO Express FPGA can be used to integrate the application engine RTL with system logic and software images created by the Xilinx Platform Studio™ tool, merging it into a single bitstream.
Change devices: The design can easily be retargeted to a different Xilinx FPGA, whether a Spartan device, a Virtex 4 device, or a Virtex 5 device. PICO Express FPGA will automatically reoptimize the implementation using the library for the new family.
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| PICO Express FPGA allows the designer to explore multiple alternatives to find the optimal performance, area, device combination. PICO Express FPGA will then create SystemC and RTL models and testbenches along with a driver for the application engine. The RTL has been optimized for a given product family and can rapidly be synthesized and integrated into the FPGA device. |
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The PICO Express FPGA allows the designer to view and trace parallelism at the task, loop, and instruction level, find and correct recurrences that limit performance, and cross probe between C and RTL to understand the implementation of the algorithm in hardware. |
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Video Filter Demonstration
PICO Express FPGA has been used to demonstrate the rapid implementation of different video filters on a Spartan-3 FPGA using an integrated design flow. The design illustrates an edge detection algorithm as well as other video filters designed in sequential C and implemented on the Xilinx Spartan-3E Display Development Kit board.
The tight integration of the Xilinx tools with PICO Express FPGA makes it easy to map the generated Xilinx-ready RTL to the target FPGA. The demonstration shows a complete flow from an untimed sequential C algorithm to FPGA hardware implementation. Detailed analysis views and performance charts pinpoint area and performance improvements. The design can be optimized for different Xilinx FPGAs through a simple change of target device, and is easily ported to create new implementations with different performance points or power profiles.
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The demonstration steps through the creation of multi-block hardware from a single, sequential C algorithm. |
Synfora – premier provider of algorithmic synthesis for SOC and FPGAs
The company has a three-pronged focus:
- Strengthen its lead on algorithmic synthesis technology.
PICO Extreme demonstrates key advances, reflecting the company’s determination to enable efficient results from complex algorithms through technology innovation and leadership. - Focus on customer deployment.
Synfora dedicates domain-knowledgeable engineers to teach and assist in deploying algorithmic synthesis on challenging projects that demonstrate the benefits of moving to a higher level. This focus provides the best way of transferring practical knowledge to the user. - Building bridges to the future.
Synfora is collaborating with industry leaders such as Coware, Synopsys, Cadence, Sequence and others to provide an integrated flow. The successful deployment of an ESL methodology depends on linking algorithmic synthesis to other ESL modeling and analysis tools. Synfora has already built reference flows with key suppliers and will continue to spearhead this effort.
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Synfora has a three pronged strategy: Continued leadership of algorithmic synthesis technology; Focus on successful customer deployment; Building bridges to the future with innovation and flows with partners |
