Synfora
has acquired Esterel Studio™, a tool suite developed
by Esterel EDA Technologies. Esterel Studio
is based on the Esterel synchronous programming language in
use for the design of control IP by three of the top 10 semiconductor
companies in SoC designs.
Esterel Studio provides
powerful capabilities for defining hierarchical,
concurrent state machines. It supports a complete flow from
design to verification and supports textual or graphical design
with animated simulation and debugging. Esterel studio is able
to generate either HDL (Verilog, VHDL) code or C / SystemC
models from the same source code, which ensures that the models
used in virtual platforms for software validation agree with
the final hardware design. Esterel Studio also supports formal
verification of the produced results, a critical
capability for complex control-oriented designs.
Esterel Studio is complementary to the PICO algorithmic synthesis
platform and is part of our long-term vision
of providing integrated design environment for both application
accelerators and more control IP.
Typical Designs Done Using
Esterel Studio
Companies such as STMicroelectronics, Texas
Instruments, NXP and Intel have used the Esterel
Studio for more than 50 production designs.
Examples include:
•
AHB, APB, OPB, OCP, AXI bus bridges, interfaces,
converter, transactors
• Cache coherence implementation and verification
• Processor architecture validation
• Processor & co-processor
• Traffic controller
• Memory architecture
• External Memory controller • Serial ATA
• DMAs
• Power management
• Video streaming
• Battery controller
• UMTS/GPRS protocol specification and verification
• Smart Cards security formal
verification
• Video controller
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