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Synfora introduces PICO Extreme
Power for Low Power Applications
Studies Show New Addition to the PICO
family Slashes Power by up to 50 Percent
Mountain View, Calif..–June 9, 2009 – Synfora,
Inc., the premier provider of algorithmic synthesis tools for integrated
circuit and system designers of large, complex processing applications,
today announced PICO Extreme Power™ to reduce power consumption,
which is a major consideration in designing mobile devices. The
new PICO Extreme Power is the industry’s first algorithmic
synthesis tool to automatically minimize power consumption at the
system-level based on a variety of techniques, including automatic
multi-level clock gating insertion. Multi-level clock gating enables
clock gating to be applied to a computation block in an application
accelerator at any level in the hierarchy. PICO Extreme Power has
delivered savings of up to 50 percent using this technique.
Researchers at Rice University were amongst the first users of
PICO Extreme Power and designed and evaluated a low-density parity
check (LDPC) decoder for the next generation wireless handset SoC.
They demonstrated a 23.5 percent reduction in dynamic power over
an identical design using a standard flow. Similarly, the Indian
Institute of Science (IISc) evaluated the effectiveness of the approach
using eight complex applications from video, imaging and wireless
domains. The results indicate as much as 50% savings in dynamic
power for executing a single task in some of the applications and
as much as 30% savings while executing a large number of tasks.
The average power reduction over all applications was 22% for a
single task and 15% over multiple tasks.
“Introducing power minimization at the system or architecture
level has a greater impact on power consumption than that implemented
at the RTL or circuit level, and adding architecture-level power
optimization capabilities to a high-level algorithmic synthesis
tool can provide significant benefits for low-power IC designs,” said
Prof. Joseph Cavallaro, Rice University. “The results of our
research clearly demonstrate that the clock gating capabilities
available with the PICO Extreme Power tool can be a major contributor
to decreasing power consumption.”
In two additional designs generated using PICO Extreme Power,
RTL level power estimates done with the Atrenta SpyGlass®-Power
solution, showed power reductions of 16 percent and 53 percent compared
with designs without block-level clock gating.
“Using SpyGlass-Power in conjunction with PICO Extreme
Power enables designers to manage power consumption early in the
design and ensure that the power savings can be measured before
the generated RTL goes to implementation. This flow has the potential
to make significant improvements in the power efficiency of SoCs,” said
Piyush Sancheti, senior director of business development at Atrenta.
In traditional RTL (Register Transfer Language) design methodologies,
inserting clock gating at a block level is usually a manual effort
because it requires the knowledge of when the block is inactive.
Using PICO Extreme Power, the designer uses directives to specify
where to insert clock gating, and PICO does the rest automatically.
As a result, PICO Extreme Power allows designers to retain all the
productivity benefits of automated synthesis and verification, including
reduced design and verification time and the ability to react very
rapidly to changes in the design specification, while optimizing
the IC power consumption.
PICO Platform
The PICO Algorithmic Synthesis Platform provides productivity
gains by creating application accelerators from an untimed C algorithm
at the highest level of abstraction. PICO yields QoR (quality of
results) that is competitive with manual design by using a unique
parallelizing compiler and multi-level hierarchical abstraction
and IP reuse. It offers the highest possible level abstraction
for large designs, and has been proven to provide huge productivity
gains on the largest production designs, not just on small blocks.
About Synfora
Synfora, Inc. is the premier provider of algorithmic synthesis
tools used to design complex systems-on-chips (SoCs) and FPGAs.
Synfora's PICO algorithmic synthesis platform offers designers
of large, complex subsystems productivity gains at the highest-level
design abstraction and delivers high QoR. Synfora serves customers
worldwide in the audio, video, imaging, wireless, and security
segments of the integrated circuit (IC) design market. The
company's investors are ATA Ventures, Foundation Capital, U.S.
Venture Partners, Wafra, and Xilinx. For the latest information
on Synfora, please visit www.synfora.com.
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