1
DO use the highest possible level abstraction (where
you can reuse the specs rather than transcribe manually) for maximal productivity
gains
<
>
2
DO focus on obtaining high QoR, equal to hand design
(or it won’t get accepted)
<
>
3
DON’T debug in RTL or you will limit abstraction
and kill key benefits
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>
4
DON’T benchmark nor define the flow on small blocks (or it won’t scale and you won’t have productivity benefits)
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>
5
DO take advantage of the high-level to optimize big things (architecture, system power, etc.)
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>
6
DO build a hierarchical methodology that will promote IP sharing and reuse (ESL makes that much easier)
<
>
7
DO assume that you will have some architecture awareness
in the code but make sure it’s at
a high level and DON’T code details (e.g. thread parallelism
or micro-architecture) in your application
<
>
8
DO build end to end flow – from algorithm to
physical design
<
>
9
DO build expertise internally, get experts to teach others (company-wide deployment in one push will create confusion and dissatisfaction)
<
>
10
DO plan for what you will want in two and five years from these tools, this methodology is here to stay (otherwise you will be quickly out-of-date and will have wasted efforts)
<
>
- Synfora
Wins Electronique’s Golden Electron Award for EDA Software
June 19, 2009 - Synfora introduces PICO Extreme Power for Low Power Applications
June 9, 2009 - Achieving
Low Power Design with Algorithmic Synthesis
Chip Design | April 9, 2009 - Use
Algorithmic Synthesis To Solve Your FPGA Prototyping And Design Issues
Electronic Design | January 29, 2009
Algorithmic Expert Blog

