Synfora's PICO C Synthesis product has achieved certification
in Berkeley Design Technology, Inc.'s (BDTI) new High Level Synthesis
Tool Certification Program™. The results show that an FPGA implementation
of a complex video motion analysis application (the BDTI Optical
Flow™ workload) using PICO C synthesis tools outperformed a traditional
DSP implementation on throughput by a factor over 30x achieving
a processing rate of 204 frames per second. The PICO implementation
required fewer code modifications to the reference code than
the DSP implementation to achieve the best performance. An important
result of the Optical Flow workload is that the overall development
efforts for the FPGA based system and the DSP based system were
comparable even though somewhat different skill sets were required.
Results on a second workload showed the PICO High Level Synthesis
tools produced results with an area efficiency comparable
to a hand-coded RTL design. On the second BDTI Work Flow, the
design implemented with the PICO High Level Synthesis platform
required only 6.4% of FPGA resources compared to 5.9% for the
hand coded design.
The BDTI High-Level
Synthesis Tool Certification Program evaluates:
- Ease of application development
- Developer productivity
- Quality of results
Results for these criteria are
obtained via comparisons of:
- High-level design tools targeting a Xilinx FPGA
- A traditional RTL-based design flow targeting a Xilinx FPGA
- A DSP software development tool suite targeting a mainstream DSP processor
For evaluation and comparison purposes, the BDTI High-Level
Synthesis Tool Certification Program (HLSTCP) uses two complex
designs; an optical flow application and a DQSPK receiver application.
Synfora obtained the HLSTCP specification from BDTI under license
and implemented the workloads, from source code to FPGA.
Workload One: Optical Flow
Workload One is an example application comprised of
a video processing application that analyzes the apparent motion
in a visual scene. Optical flow is used in various applications,
including motion detection, object segmentation, time-to-collision
calculations, motion compensated encoding, and stereo disparity
measurement. Such applications are used for computer vision
in video surveillance, vehicle driver assistance, and security
and mil-aero systems.
Workload Two: DQPSK Receiver
Workload Two is an example application software module comprised
of a differential quaternary phase shift keying (DQPSK) demodulator
receiver. DQPSK is used in high bitrate communications systems.
BDTI High-Level Synthesis Tool Certification Program Results
BDTI Optical Flow Workload
Operating Point 1: Fixed Workload, 720p Resolution
(1280 x 720 Progressive Scan, 60 frames per second)
Synfora PICO plus Xilinx RTL
tools targeting a Xilinx XC3SD3400A FPGA |
$26.65 |
39.6% |
Texas Instruments software development
tools targeting a
TMS320DM6437 DSP processor |
$21.25 |
N/A
(a minimum of 12 DSPs would be
required to meet this operating point) |
BDTI High-Level Synthesis Tool Certification Program
BDTI Optical Flow Workload
Operating Point 2: Maximum Frame Rate Achievable
at
720p Resolution (1280 x 720 Progressive Scan)
Synfora PICO plus Xilinx RTL
tools targeting a Xilinx XC3SD3400A FPGA |
$26.65 |
204 fps |
$0.13 |
Texas Instruments software development
tools targeting a
TMS320DM6437 DSP processor |
$21.25 |
5.1 fps |
$4.16 |
BDTI High-Level Synthesis Tool Certification Program
Results
BDTI DQPSK Receiver Workload
Fixed Workload, 18.75 Msamples/second input
data with a 75 MHz clock speed
| Synfora PICO plus Xilinx RTL tools targeting
a Xilinx XC3SD3400A FPGA |
6.4 % |
| Hand-written RTL code using Xilinx RTL
tools targeting a Xilinx XC3SD3400A FPGA. |
5.9 % |
For more information on
BDTI’s HLSTCP results for Synfora PICO see http://www.bdti.com/bdtimark/hlstcp_synfora.html.
